SystemVerilog stubs generation #45
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The next commit should fix the existing CI to |
ssmolov
reviewed
Aug 8, 2024
README.md
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| @@ -217,6 +218,7 @@ The list of arguments for `hls`-mode is presented below: | |||
| * `-h,--help`: *optional* flag; used to print the help-message about other arguments. | |||
| * `--config <PATH>`: *required* filesystem-path option; used to specify the file for a JSON latency configuration file. Its format is presented in *JSON Configuration* section. | |||
| * `--out-sv <PATH>`: *optional* filesystem-path option; used to specify the output SystemVerilog file. | |||
| * `--out-sv-stubs <PATH>`: *optional* filesystem-path option; used to specify the output file for generated SystemVerilog stubs. | |||
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out-sv-stubs -> out-sv-lib
"the output file for generated SystemVerilog stubs" -> "the output SystemVerilog file for generated operations library"
config.json
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| @@ -4,6 +4,7 @@ | |||
| "asap_scheduler" : false, | |||
| "lp_scheduler" : false, | |||
| "out_sv" : "", | |||
| "out_sv_stubs" : "", | |||
| @@ -37,4 +37,18 @@ def DFCIRLinearSchedulerPass: Pass<"dfcir-linear-scheduler-pass", "mlir::ModuleO | |||
| let constructor = "mlir::dfcir::createDFCIRLinearSchedulerPass()"; | |||
| } | |||
|
|
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| def FIRRTLStubGeneratorPass: Pass<"firrtl-stub-generator-pass", "mlir::ModuleOp"> { | |||
| let summary = "Generate stubs for pipelined computational modules, specified in FIRRTL."; | |||
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"Generate stubs for pipelined computational modules, specified in FIRRTL." -> ""Generate stub modules for pipelined computational operations.""
| // | ||
| // Part of the Utopia HLS Project, under the Apache License v2.0 | ||
| // SPDX-License-Identifier: Apache-2.0 | ||
| // Copyright 2021-2024 ISP RAS (http://www.ispras.ru) |
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Fixed here and in templates/stubs.tpl.
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| } else { | ||
| result->SetValue("OP", "*"); | ||
| } |
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Add separate branch for MUL operation, report an error ("Unsupported module: " ?) at the default branch
| @@ -62,6 +62,7 @@ enum Scheduler { | |||
| // Used for accessing specified output format paths. | |||
| enum class OutputFormatID : uint8_t { | |||
| SystemVerilog = 0, | |||
| SVStubs, | |||
src/options.h
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| @@ -36,6 +36,7 @@ | |||
| #define ASAP_SCHEDULER_JSON "asap_scheduler" | |||
| #define LP_SCHEDULER_JSON "lp_scheduler" | |||
| #define OUT_SV_JSON "out_sv" | |||
| #define OUT_SV_STUBS_JSON "out_sv_stubs" | |||
src/options.h
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| @@ -49,6 +50,7 @@ | |||
| #define LP_SCHEDULER_FLAG CLI_FLAG("l") | |||
| #define OUTPUT_GROUP "output" | |||
| #define OUT_SV_ARG CLI_ARG("out-sv") | |||
| #define OUT_SV_STUBS_ARG CLI_ARG("out-sv-stubs") | |||
src/options.h
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| outputGroup->add_option(OUT_SV_STUBS_ARG, | ||
| outNames[OUT_FORMAT_ID_INT(SVStubs)], | ||
| "Path to output stubs for SystemVerilog modules"); |
src/options.h
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| @@ -198,6 +203,7 @@ struct HlsOptions final : public AppOptions { | |||
| get(json, ASAP_SCHEDULER_JSON, asapScheduler); | |||
| get(json, LP_SCHEDULER_JSON, lpScheduler); | |||
| get(json, OUT_SV_JSON, outNames[OUT_FORMAT_ID_INT(SystemVerilog)]); | |||
| get(json, OUT_SV_STUBS_JSON, outNames[OUT_FORMAT_ID_INT(SVStubs)]); | |||
Muxianesty
commented
Aug 8, 2024
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This Pull Request introduces a new option for Utopia HLS CLI to generate stub modules for SystemVerilog, which can be useful in SystemVerilog syntax parsing (e.g. with Verilator).